Conventional programmable microprocessors of the related art sequentially read instructions stored in memories, and successively process the instructions. The instructions that are able to be performed are simple instructions. There is a certain limit to processing capability of such microprocessors.
In recent years, regarding microprocessors, in addition to existing demands including the demand for fast responses to interrupts and so forth, there has also been a demand for performance of more complicated arithmetic processes at a high speed.
Generally, control microcomputers are designed with the aim of realizing control using interrupts and fast responses to the interrupts, differently from general-purpose microprocessors (central processing units (CPUs)) that are designed with the aim of performing arithmetic processes at a high speed. For this reason, there is a problem that instructions which are able to be performed by the control microcomputers include only simple instructions and do not include complicated instructions. Furthermore, even when instructions which are able to be performed by the control microcomputers include complicated instructions, there is a problem that the times taken to perform the complicated instructions are long. Responses to interrupts are considered as an important feature of control micro processors that have been desired in recent years. However, in addition to the demand for responses to interrupts, there has been a demand for being able to perform an application including complicated arithmetic processes at a high speed. Microprocessors, including control microprocessors, have the following problems.
When performance of a complicated arithmetic process is made possible using such a microprocessor, lengthy latency for the arithmetic process occurs in an arithmetic logic unit (ALU) that is provided in the microprocessor. Accordingly, slow response times to an interrupt when the arithmetic process is performed are problematic. Furthermore, when an arithmetic process that is being performed is terminated because of the slow response, an increasing penalty is incurred by re-performing the arithmetic process. Accordingly, the time taken to perform the arithmetic process is problematically increased.
For this reason, a configuration has been used, in which a coprocessor that is dedicated to the performance of complicated arithmetic processes is connected to a processor. In this configuration, the coprocessor performs complicated arithmetic processes, and the processor receives only results of the arithmetic processes. The coprocessor is connected on a general-purpose bus. In such an arrangement, certain arithmetic processes that are included in an application may be continuously performed, such as when an arithmetic process uses a result of the immediately previous arithmetic process or when a result of an arithmetic process is necessary immediately after the arithmetic process is performed. In such a case, even when, for example, only one arithmetic process using a square root is performed by the coprocessor, there is a problem because the capability of performing arithmetic processes is not markedly improved in reality because of a penalty incurred by bus access. Furthermore, when a coprocessor is connected to a general-purpose bus, processing is negatively influenced by responses to interrupts and so forth, and the time taken to process interrupts is problematically increased.
Furthermore, when a coprocessor is connected to a processor using a dedicated interface (I/F), arithmetic processes that are able to be performed are determined based on instructions that are implemented in the connected coprocessor. Accordingly, there is a problem because arithmetic processes which are able to be used are limited.
Arithmetic devices capable of being reconfigured to solve the problem of a coprocessor's limited arithmetic function are known. An arithmetic device capable of being reconfigured includes a plurality of processor elements and an inter-processor-element network in which the plurality of processor elements are connected to input terminals and output terminals so that connection therebetween is able to be changed. The internal state of the arithmetic device capable of being reconfigured is able to be changed so that a plurality of arithmetic functions are selectively performed. Japanese Laid-open Patent Publications No. 2006-302132, No. 2007-094847, and No. 2007-133456 describe arithmetic devices whose internal state is able to be changed as described above and which are capable of being reconfigured. Hereinafter, arithmetic devices capable of being reconfigured are referred to as “reconfigurable arithmetic devices”.
Generally, reconfigurable arithmetic devices aim to perform complicated arithmetic processes. Accordingly, the reconfigurable arithmetic devices are configured so that a large number of pieces of variable data are able to be set and an arithmetic process is able to be repeatedly performed. Thus, arithmetic processes that are performed in the reconfigurable arithmetic devices take long times, and it is not strictly necessary that the reconfigurable arithmetic devices be accessed by processors at a high speed. For this reason, typically, such a reconfigurable arithmetic device is connected to a general-purpose bus, and the reconfigurable arithmetic device is activated using an interrupt after a processor (CPU) sets variable data. When reconfigurable arithmetic devices are used, processors are referred to as “CPUs”. Accordingly, hereinafter, description is made supposing that processors are CPUs.
The arithmetic function of reconfigurable arithmetic devices is able to be changed, and the reconfigurable arithmetic devices are capable of performing very complicated arithmetic processes. When the internal configuration of the reconfigurable arithmetic devices is changed, the reconfigurable arithmetic devices are capable of performing comparatively simple arithmetic processes. When such comparatively simple arithmetic processes are performed by CPUs, the time taken to perform the comparatively simple arithmetic processes is increased. Regarding use of the reconfigurable arithmetic devices in reality, the reconfigurable arithmetic devices are not often used to perform very complicated arithmetic processes. The reconfigurable arithmetic devices are often used to perform comparatively simple arithmetic processes.
The above-described reconfigurable arithmetic device is connected to a general-purpose bus. In reality, the ability to perform arithmetic processes is not markedly improved because of the above-described penalty incurred by bus access. There is also a problem due to the increased amount of time taken to process interrupts. For this reason, even when the comparatively simple arithmetic processes are performed by the reconfigurable arithmetic device, it is difficult to reduce the amount of time taken to perform the arithmetic processes.